Currently, an eight mask process flow is used to manufacture etch stop oxide thin film transistors devices. Forming a viahole that connects to the first metal layer in such a process typically requires long dry etching time through a number of passivation layers and through the gate insulation layer. A viahole dry etch process of this magnitude presents several difficulties including photoresist stability during the long time dry etch, tapper and undercut issues the can impact one or more layers in multi SiNx/SiO2 stacks, and the possibility of damage to the device due to an electrostatic discharge. Thus, there is a need for an improved viahole etch process that can be used to connected to signal lines that are routed in the first metal layer.